/* $Id$ */
/* vim: set filetype=verilog ts=8 sw=4 tw=132: */
/*****************************************************************************
 
              (c) Copyright 1987 - 2012,  VIA Technologies, Inc.       
                            ALL RIGHTS RESERVED                            
                                                                     
 This design and all of its related documentation constitutes valuable and
 confidential property of VIA Technologies, Inc.  No part of it may be
 reproduced in any form or by any means   used to make any transformation
 / adaptation / redistribution without the prior written permission from the
 copyright holders. 
 
------------------------------------------------------------------------------

  DESCRIPTION:

  FEATURES:

  TODO:

  AUTHORS:
     Shawn Fang
    
------------------------------------------------------------------------------
                             REVISION HISTORY
    $Log$

*****************************************************************************/
module wrtbak
    (
	//output
		     output [3:0] w_icode    ,//        (w_icode[2:0]),
                     output [31:0] w_valM   ,//          (w_valM[31:0]),
                     output [31:0] w_valE  ,//           (w_valE[31:0]),
                     output [3:0] w_dstM    ,//         (w_dstM[3:0]),
                     output [3:0] w_dstE    ,//         (w_dstE[3:0]),
                     output reg[2:0] w_stat   ,//          (w_stat[2:0]),
                     // Inputs
                     input  clock,//             (clock),
                     input  reset      ,//        (reset),
                     input  [3:0] m_icode ,//           (m_icode[2:0]),
                     input  [31:0] m_valM ,//            (m_valM[31:0]),
                     input  [31:0] m_valE,//             (m_valE[31:0]),
                     input  [3:0] m_dstM  ,//           (m_dstM[3:0]),
                     input  [3:0] m_dstE ,//            (m_dstE[3:0]),
                     input  [2:0] m_stat,   //          (m_stat[2:0])
		     input  W_stall,
		     input  W_bubble
    );
ppregs_W U_ppregs_W
    (
	.clock(clock),
	.reset(reset),
	.W_stall(W_stall),
        .W_bubble(W_bubble),
	.icode_i(m_icode),
	.dstE_i(m_dstE),
	.dstM_i(m_dstM),
	.valE_i(m_valE),
	.valM_i(m_valM),
	
	.icode_o(w_icode),
	.dstE_o(w_dstE),
	.dstM_o(w_dstM),
	.valM_o(w_valM),
	.valE_o(w_valE)
	    );
always @ (posedge clock or posedge reset)
    begin
	if(reset)
	begin
	    w_stat<=`SAOK;
	end
	else
	begin
	    if(W_stall)
		w_stat<=w_stat;
	    else if(W_bubble)
		w_stat<=`SAOK;
	    else if(w_icode==`IHALT)
		w_stat<=`SHLT;
	    else
		w_stat<=m_stat;
	end
    end

endmodule
